In the PNNI routing and signaling protocol for ATM networks, switching nodes are organized into logical peer groups. Each node in a peer group has full details of the topology of that peer group, but only summary knowledge of the topology of other peer groups. Each ATM node requires a 160 bit address, called the ATM end system address (AESA), defined by the ATM Forum. All nodes in a given peer group have, for some value of k, where 0<=k<=104, identical values of the first k bits in their node AESAs. This value of k is called the PNNI level indicator. Judicious definition of peer groups and their corresponding level of PNNI hierarchy can create a logical partitioning of the ATM switches that increases PNNI routing efficiency and performance. A peer group with more than one node can itself be partitioned, leading to a tree representation of the hierarchies. When designing a hierarchy, nodes are often assigned to peer groups to form geographic clusters. If the hierarchy is not appropriately defined, changing it may require changing the AESA, which results in a temporary loss of service to customers. This leads to the problem of node partitioning to support both a current view of the hierarchy as well as possible future creation of both lower level and higher level peer groups.
Therefore, a need exists for a method and apparatus to effectively design hierarchical node partitions in a PNNI network using ATM End System Addresses (AESAs).